[LLVMdev] Adding masked vector load and store intrinsics

shahid shahid shahid77c at yahoo.com
Sat Oct 25 07:53:04 PDT 2014

 Hi Elena,
Nice to see that your thinking are quite similar with mine.
Do you plan to generate this intrinsic in Loop Vectorizer based on subtarget feature?
If so, it would be better to let it generate here in target independent manner.Later on,during lowering, based on the availability of target support for masked ops you can decideeither to scalarize or generate the target masked ops instruction.

     On Friday, October 24, 2014 4:59 PM, "Demikhovsky, Elena" <elena.demikhovsky at intel.com> wrote:

  <!--#yiv1368802508 .yiv1368802508EmailQuote {margin-left:1pt;padding-left:4pt;border-left:#800000 2px solid;}-->Hi, We would like to add support for masked vector loads and stores by introducing new target-independent intrinsics. The loop vectorizer will then be enhanced to optimize loops containing conditional memory accesses by generating theseintrinsics for existing targets such as AVX2 and AVX-512. The vectorizer will first ask the target about availability of masked vector loads and stores. The SLP vectorizer can potentially be enhanced to use these intrinsics as well. The intrinsics would be legal for all targets; targets that do not support masked vector loads or stores will scalarize them.The addressed memory will not be touched for masked-off lanes. In particular, if all lanes are masked off no address will be accessed.   call void @llvm.masked.store (i32* %addr, <16 x i32> %data, i32 4, <16 x i1> %mask)   %data = call <8 x i32> @llvm.masked.load (i32* %addr, <8 x i32> %passthru, i32 4, <8 x i1> %mask) where %passthru is used to fill the elements of %data that are masked-off (if any; can be zeroinitializer or undef). Comments so far, before we dive into more details? Thank you. - Elena and Ayal  ---------------------------------------------------------------------
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