[LLVMdev] Adding masked vector load and store intrinsics

dag at cray.com dag at cray.com
Fri Oct 24 12:55:38 PDT 2014

"Smith, Kevin B" <kevin.b.smith at intel.com> writes:

> I strongly agree with all these reasons, and it is for all those
> reasons that the proposal is written this way.

Once general loads and store intrinsics are added we really do need to
address more general masking.  Nearly every floating-point operation can
trap, so those need masking available.  Integer operations like divide
will also need masking.  Either we will need a generalized masked
intrinsic for each such operation (e.g. llvm.masked.fadd) or we need a
more general way to represent masks in LLVM IR.  We had such a
discussion some years ago but it didn't really go anywhere.

Adding general mask intrinsics for operations that can trap seems like
the easiest way to make forward progress.


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