[LLVMdev] Adding masked vector load and store intrinsics

[Tian, Xinmin]

Ditto 

Xinmin Tian

-----Original Message-----
From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] On Behalf Of Smith, Kevin B
Sent: Friday, October 24, 2014 11:14 AM
To: dag at cray.com; Hal Finkel
Cc: llvmdev at cs.uiuc.edu
Subject: Re: [LLVMdev] Adding masked vector load and store intrinsics

I strongly agree with all these reasons, and it is for all those reasons that the proposal is written this way.

Kevin B. Smith

-----Original Message-----
From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] On Behalf Of dag at cray.com
Sent: Friday, October 24, 2014 10:39 AM
To: Hal Finkel
Cc: llvmdev at cs.uiuc.edu
Subject: Re: [LLVMdev] Adding masked vector load and store intrinsics

Hal Finkel <hfinkel at anl.gov> writes:

>> > Nevermind ;) -- I changed my mind, the safety issue is with 
>> > non-aligned loads that might cross page boundaries. Is that right?
>> 
>> That's just one safety issue.  There are others.
>
> Can you be more specific? You mentioned overindexing in your other 
> e-mail, exactly what do you mean by that?

Accessing past the end of an array.  Some vector optimizations do that and assume the masking will prevent traps.  Aggressive vectorizers can do all kinds of "unsafe" transformations that are safe in the presence of masks.

Any time there is control flow in the loop protecting a dereference of a NULL pointer, a mask is needed and it needs to be applied at the time of the load, not at the time of the write to the loaded-to register.
That's why select doesn't work.  This same issues extends to any trap situation like a divide-by-zero or use of a NaN.  It's not only the write to the register that needs protection, it's the operation itself.

                              -David

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