[LLVMdev] Adding masked vector load and store intrinsics

Tian, Xinmin xinmin.tian at intel.com
Fri Oct 24 10:57:48 PDT 2014

> select(mask, load(addr), passthru)?

David is right,  "select(mask, load(addr), passthru)"  is like vector load + blending ... which involves memory access speculation, and not safe in some cases, so it does not have same semantics of masking-lane-off,  


-----Original Message-----
From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] On Behalf Of dag at cray.com
Sent: Friday, October 24, 2014 9:49 AM
To: Hal Finkel
Cc: llvmdev at cs.uiuc.edu
Subject: Re: [LLVMdev] Adding masked vector load and store intrinsics

Hal Finkel <hfinkel at anl.gov> writes:

> For the loads, I'm must less sure. Why can't we represent the loads as 
> select(mask, load(addr), passthru)?

Because that does not specify the correct semantics.  This formulation expects the load to happen before the mask is applied.  The load could trap.  The operation needs to be presented as an atomic unit.

The same problem exists with any potentially trapping instruction (e.g. all floating point computations).  The need for intrinsics goes way beyond loads and stores.

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