[LLVMdev] Adding masked vector load and store intrinsics

[dag at cray.com]

Hal Finkel <hfinkel at anl.gov> writes:

> For the loads, I'm must less sure. Why can't we represent the loads as
> select(mask, load(addr), passthru)?

Because that does not specify the correct semantics.  This formulation
expects the load to happen before the mask is applied.  The load could
trap.  The operation needs to be presented as an atomic unit.

The same problem exists with any potentially trapping instruction
(e.g. all floating point computations).  The need for intrinsics goes
way beyond loads and stores.

                             -David