[LLVMdev] Adding masked vector load and store intrinsics
hfinkel at anl.gov
Fri Oct 24 09:58:19 PDT 2014
----- Original Message -----
> From: dag at cray.com
> To: "Hal Finkel" <hfinkel at anl.gov>
> Cc: "Elena Demikhovsky" <elena.demikhovsky at intel.com>, llvmdev at cs.uiuc.edu
> Sent: Friday, October 24, 2014 11:56:14 AM
> Subject: Re: [LLVMdev] Adding masked vector load and store intrinsics
> Hal Finkel <hfinkel at anl.gov> writes:
> >> If this were really a question of safety, I'd agree. And if we
> >> were
> >> talking about gather loads, I'd agree. For a regular vector loads,
> >> I
> >> don't see this as a safety issue. We should outline what the
> >> downside of emitting a regular load would actually be should some
> >> optimization be done to the select. Can you please elaborate on
> >> this?
> > Nevermind ;) -- I changed my mind, the safety issue is with
> > non-aligned loads that might cross page boundaries. Is that right?
> That's just one safety issue. There are others.
Can you be more specific? You mentioned overindexing in your other e-mail, exactly what do you mean by that?
> > If so, I think this proposal is good (although obviously the docs
> > need
> > to make clear what the faulting behavior of these intrinsics is).
> The behavior should be not to ever fault on an element whose mask bit
> false, and behave as a regular load (wrt trapping) for any element
> mask bit is true.
Assistant Computational Scientist
Leadership Computing Facility
Argonne National Laboratory
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