[LLVMdev] Adding masked vector load and store intrinsics

dag at cray.com dag at cray.com
Fri Oct 24 09:56:14 PDT 2014

Hal Finkel <hfinkel at anl.gov> writes:

>> If this were really a question of safety, I'd agree. And if we were
>> talking about gather loads, I'd agree. For a regular vector loads, I
>> don't see this as a safety issue. We should outline what the
>> downside of emitting a regular load would actually be should some
>> optimization be done to the select. Can you please elaborate on
>> this?
> Nevermind ;) -- I changed my mind, the safety issue is with
> non-aligned loads that might cross page boundaries. Is that right?

That's just one safety issue.  There are others.

> If so, I think this proposal is good (although obviously the docs need
> to make clear what the faulting behavior of these intrinsics is).

The behavior should be not to ever fault on an element whose mask bit is
false, and behave as a regular load (wrt trapping) for any element whose
mask bit is true.


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