[LLVMdev] Lowering to return multiple values: codeGen, instruction write one value to the input register.

kewuzhang kewu.zhang at amd.com
Fri Jul 11 12:11:26 PDT 2014


Hi Tim, 

Thank you for the quick answer.
basically my first step is to solve the my_sincos(v4f32). which returns sin and cos results into two separate vector registers.
I have sin, and cos target instructions.

so my plan is to lower it like the following when I see the “sincos(v4f32)” node.
“
SDValue sin  = DAG.getNode(my_ISD::sin, DL, VT, Op.getOperand(0);
SDValue cos = DAG.getNode(my_ISD::cos, DL, VT, Op.getOperand(0);

SDValue sinVal = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v4f32, sin, sin, sin, sin);
SDValue cosVal = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v4f32, cos, cos, cos, cos);

SDValue results[] = {sinVal, cosVal};
return DAG.getMergeValues(results, 2, DL);
"

So in a test, I am expecting  the my_sincos(v4f32) node should appears have two return values in view-dag-combine1-dags even I am using only sinVal.

best

Kevin


On Jul 11, 2014, at 2:11 PM, Tim Northover <t.p.northover at gmail.com> wrote:

> Hi Kevin,
> 
> It's quite difficult to tell exactly what's going wrong here without
> more context. If you could post a screenshot (or similar) of the
> viewDAG output before and after, that would be very helpful. Or
> describe in more detail what you're expecting to see but don't.
> 
> On 11 July 2014 18:59, kewuzhang <kewu.zhang at amd.com> wrote:
>> …….
>> SDValue z = DAG.getNode(my_ISD::test_op, DL, VT, Op.getOperand(0);
>> SDValue w = DAG.getConstant(1, MVT::i32);
>> 
>> SDValue DataZ = DAG.getNode(ISD::BUILDER_VECTOR, DL, MVT::v4i32, z, z, z,
>> z);
>> SDValue DataW = DAG.getNode(ISD::BUILDER_VECTOR, DL, MVT::v4i32, w, w, w,
>> w);
>> SDValue result[] = {DataZ, DataW};
>> return DAg.getMergeValues(results, 2, DL);
>> 
>>>> but my view-dag only shows one return value,  wondering what is wrong?
>> should the results dags must be somehow “dependent” on each other?
> 
> However, as a very rough guess: did the input node have two outputs?
> If not, then the second result of the merge node will be unused and
> might appear not to be there.
> 
> Cheers.
> 
> Tim.





More information about the llvm-dev mailing list