[LLVMdev] Representing 2 FUs mapped to same slot in Tablegen

[Pankaj Gode]

Hi All,

I have a query regarding, how should one represent mapping of functional units to same slot in Tablegen ?

For example, if my Functional units are defined in TargetSchedule.td, as:

def fu0 : FuncUnit;
def fu1 : FuncUnit;

def f_fu0 : FuncUnit;

def f_fu1 : FuncUnit;


def myprocItineraries:
  ProcessorItineraries<[fu0, fu1, f_fu0, f_fu1], [], [
    ... 

      ]>;  


def myProcModel : SchedMachineModel {
  let IssueWidth = 2;
...
}


I could not find a way to represent that, in 'Issue Slot 0', I want to use either 'fu0 or f_fu0', while scheduling.
I would need this when, for example I want to use f_fu0 for some operation in slot0, instead of fu0. 

I understand that ProcessorItineraries<[fu0, fu1, f_fu0, f_fu1] ... 
allows me to specify that instruction scheduled in issue slot 0 will be executed on fu0 and instruction to execute on f_fu0 can be scheduled in slot 2 only. 
While scheduling an operation, I would be using InstructionItineraries to check whether the operation can be executed on which FuncUnit,
but I would need extra logic to maintain that operation executing on 'fu0 or f_fu0' can be scheduled in slot 0.

Thus, specifying the processor itineraries as above will be a wrong representation my this case.
Or, should I be specifying this information somewhere 
Or, it is fine to take care of this while scheduling ?

Please correct me if I have wrong understanding.


Regards,
Pankaj
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