[LLVMdev] Load Instruction that changes value of two registers
tima0900 at googlemail.com
Tue Jan 28 19:49:10 PST 2014
**thanks for the answer. Sadly I didn't completely get it.*
> Hi Markus,
> On Jan 28, 2014, at 3:30 PM, Markus Timpl <tima0900 at googlemail.com
> <mailto:tima0900 at googlemail.com>> wrote:
>> I'm writing a backend for an architecture that only has LOAD
>> Instructions that first copy the old value of the target register in
>> another register and after that load the provided value into the
> If I understand correctly, your load performs in parallel a copy and a
> loadedVal<dstReg> load addr || <someReg> copy <dstReg>
*Yes, it does exactly that. It first copies the old register value and
then performs a "nomal" load.*
*Let me give some more details about the target platform:**
**It only has 2 useable registers(AKKU1 and AKKU2), it also has a status
register but that doesn't matter in this case.**
**It's only possible to directly load values into the AKKU1 register and
each load into AKKU1 first copies the old AKKU1 value into AKKU2.**
**The only way to get a value into AKKU2 is to first load it into AKKU1
and then copy it(can be done via another AKKU1 load or a copy instruction).*
*There are possibilities to get a value into AKKU1/AKKU2 without
changing the value of AKKU2/AKKU1 but they involve a couple of simple
that's why I don't want to it that way(runtime of the code would be
> If you forget about the copy part, you can simply model your load like
> <dstReg>, <someReg> load addr
> <someReg> will be an implicit definition and your good to go.
> Obviously, this is not optimal.
*Do you mean a TableGen match pattern like this(AKKU1 and AKKU2 are
**[**(set (AKKU1:$dst, AKKU2:$dst2), (load addr:$addr))**]**
**That obviously isn't a valid pattern...**So I don't understand how to
put that into a valid pattern...**
**Also wouldn't LLVM think that AKKU2 has the same value as AKKU1 after
the operation and not a trash value?*
> Note that, the original code (dot = load addr) does not define
> <someReg>, so I guess you have some rules to assign it (like <sameReg>
> = <dstReg> + 1).
> Therefore you may have to create a specific register class for that:
> <BigDstReg> load addr
> <dstReg> = BigDstReg.subIdx
> And have a pattern using a EXTRACT_SUBREG (see ARM NEON).
*So <BigDstReg> will be AKKU1 and AKKU2, and I would do sth like that as
[(set (EXTRACT_SUBREG BigDestReg:$BigDestReg, 1), (load addr:$addr)]
*Is that correct? LLVM will assume that the other part of the register
is trash after the instruction?*
> Now, if you want to remember that <someReg> is not some trash value
> but contains the value of <dstReg> before this instruction, this is a
> different story.
> The tricky part here is how do you tell the compiler where does dstReg
> come from? Indeed, you will know that, only when you will choose it.
> You could make this choice a priori, but this is not optimal either.
> Anyhow, I do not think there is a straight answer for your case.
> Note: I was assuming that reg2 depends on the choice of reg1, if it is
> not the case, then, this is slightly a different story.
*Maybe it would be easier to take control of the DAG to MachineInstr
step and arrange the instruction in a valid way?
Do you think that is a good idea? The register allocation should be
pretty easy with only two registers...
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