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<div class="moz-cite-prefix"><b>Hello Quentin,</b><b><br>
</b><b>
thanks for the answer. Sadly I didn't completely get it.</b><br>
<br>
</div>
<blockquote
cite="mid:8351E2B3-83ED-4D90-B93B-10094D0E67D3@apple.com"
type="cite">Hi Markus,<br>
<div apple-content-edited="true"> </div>
<br>
<div>
<div>On Jan 28, 2014, at 3:30 PM, Markus Timpl <<a
moz-do-not-send="true" href="mailto:tima0900@googlemail.com">tima0900@googlemail.com</a>>
wrote:</div>
<br class="Apple-interchange-newline">
<blockquote type="cite">
<div dir="ltr">
<div>Hello,</div>
<div>I'm writing a backend for an architecture that only has
LOAD Instructions that first copy the old value of the
target register in another register and after that load
the provided value into the register. </div>
</div>
</blockquote>
<div>If I understand correctly, your load performs in parallel a
copy and a load:</div>
<div>loadedVal<dstReg> load addr || <someReg> copy
<dstReg> <br>
</div>
</div>
</blockquote>
<br>
<b>Yes, it does exactly that. It first copies the old register value
and then performs a "nomal" load.</b><br>
<br>
<b>Let me give some more details about the target platform:</b><b><br>
</b><b>
It only has 2 useable registers(AKKU1 and AKKU2), it also has a
status register but that doesn't matter in this case.</b><b><br>
</b><b>
It's only possible to directly load values into the AKKU1 register
and each load into AKKU1 first copies the old AKKU1 value into
AKKU2.</b><b><br>
</b><b>
The only way to get a value into AKKU2 is to first load it into
AKKU1 and then copy it(can be done via another AKKU1 load or a
copy instruction).</b><br>
<b>There are possibilities to get a value into AKKU1/AKKU2 without
changing the value of AKKU2/AKKU1 but they involve a couple of
simple instructions and<br>
that's why I don't want to it that way(runtime of the code would
be quite bad).<br>
</b>
<blockquote
cite="mid:8351E2B3-83ED-4D90-B93B-10094D0E67D3@apple.com"
type="cite">
<div>
<div><br>
</div>
<div>If you forget about the copy part, you can simply model
your load like this:</div>
<div><dstReg>, <someReg> load addr</div>
<div><br>
</div>
<div><someReg> will be an implicit definition and your
good to go.</div>
<div>Obviously, this is not optimal.</div>
</div>
</blockquote>
<br>
<b>Do you mean a TableGen match pattern like this(AKKU1 and AKKU2
are register classes):</b><b><br>
</b><b>[</b><b><font face="Consolas"><font face="Consolas">(set
(AKKU1:$dst, AKKU2:$dst2), (load addr:$addr))</font></font></b><b>]</b><b><br>
</b><b><br>
</b><b>That obviously isn't a valid pattern...</b><b> So I don't
understand how to put that into a valid pattern...</b><b><br>
</b><b>Also wouldn't LLVM think that AKKU2 has the same value as
AKKU1 after the operation and not a trash value?</b><br>
<br>
<blockquote
cite="mid:8351E2B3-83ED-4D90-B93B-10094D0E67D3@apple.com"
type="cite">
<div>
<div><br>
</div>
<div>Note that, the original code (dot = load addr) does not
define <someReg>, so I guess you have some rules to
assign it (like <sameReg> = <dstReg> + 1).</div>
<div>Therefore you may have to create a specific register class
for that:</div>
<div><BigDstReg> load addr</div>
<div><dstReg> = BigDstReg.subIdx</div>
<div>And have a pattern using a EXTRACT_SUBREG (see ARM NEON).</div>
<div><br>
</div>
</div>
</blockquote>
<br>
<b>So <BigDstReg> will be AKKU1 and AKKU2, and I would do sth
like that as match pattern:<br>
[(set (EXTRACT_SUBREG BigDestReg:$BigDestReg, 1), (load
addr:$addr)]<br>
</b><br>
<b>Is that correct? LLVM will assume that the other part of the
register is trash after the instruction?</b><br>
<br>
<blockquote
cite="mid:8351E2B3-83ED-4D90-B93B-10094D0E67D3@apple.com"
type="cite">
<div>
<div><br>
</div>
<div>Now, if you want to remember that <someReg> is not
some trash value but contains the value of <dstReg>
before this instruction, this is a different story.</div>
<div><br>
</div>
<div>The tricky part here is how do you tell the compiler where
does dstReg come from? Indeed, you will know that, only when
you will choose it.</div>
<div>You could make this choice a priori, but this is not
optimal either.</div>
<div>Anyhow, I do not think there is a straight answer for your
case.</div>
<div><br>
</div>
<div>Note: I was assuming that reg2 depends on the choice of
reg1, if it is not the case, then, this is slightly a
different story.</div>
<div><br>
</div>
<div>-Quentin</div>
<div><br>
</div>
</div>
</blockquote>
<b>Maybe it would be easier to take control of the DAG to
MachineInstr step and arrange the instruction in a valid way?<br>
Do you think that is a good idea? The register allocation should
be pretty easy with only two registers...<br>
<br>
Thanks again,<br>
Markus</b><br>
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