[LLVMdev] Does Mips resolve hazard in pre-ra-sched or post-ra-sched?
ahatanak at gmail.com
Thu Sep 19 14:39:49 PDT 2013
Mips invokes the post-RA scheduler only when OptLevel > Aggressive, so you
will have to compile with -O3.
You can also invoke the MI (pre-RA) scheduler with llc option
"-enable-misched". As you have pointed out, the post-isel scheduler is
mandatory, and therefore you don't have to give any command line options.
Currently, mips has only one generic scheduling itinerary model in
MipsSchedule.td that is not tailored to any specific core, so you might
have to tweak it to have the scheduler generate efficient code for your
On Wed, Sep 18, 2013 at 7:41 PM, Liu Xin <navy.xliu at gmail.com> wrote:
> Hi, LLVM,
> I found LLVM codegen has 3 passes for instruction scheduling:
> 1) pre-ra sched
> 2) post-ra sched
> 3) mi sched.
> for RISC machines, there are data hazard cases appear only after Register
> Allocation(RA). for example, $t0 is used immediately after writing(RAW):
> ld $t0, MEM
> add $t2, $t0, $0
> There may be one or more stall in pipeline. Instruction scheduler can
> detect this kinds of conflict and insert other instructions to avoid
> pipeline bubble. I think this work only can be done after RA. If so,
> what's the purpose for 1). I found 1) is mandatory and 2/3) are optional.
> Further, at least one target enable pre-RA-sched with harzardRecognizer.
> Does it really work out? you can resolve data hazard using pre-RA-sched
> LLVM Developers mailing list
> LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu
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