[LLVMdev] Does Mips resolve hazard in pre-ra-sched or post-ra-sched?
navy.xliu at gmail.com
Wed Sep 18 19:41:51 PDT 2013
I found LLVM codegen has 3 passes for instruction scheduling:
1) pre-ra sched
2) post-ra sched
3) mi sched.
for RISC machines, there are data hazard cases appear only after Register
Allocation(RA). for example, $t0 is used immediately after writing(RAW):
ld $t0, MEM
add $t2, $t0, $0
There may be one or more stall in pipeline. Instruction scheduler can
detect this kinds of conflict and insert other instructions to avoid
pipeline bubble. I think this work only can be done after RA. If so,
what's the purpose for 1). I found 1) is mandatory and 2/3) are optional.
Further, at least one target enable pre-RA-sched with harzardRecognizer.
Does it really work out? you can resolve data hazard using pre-RA-sched
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