[LLVMdev] Definition of RegisterClass for load instruction in Thumb2
grosbach at apple.com
Wed May 29 13:22:17 PDT 2013
On May 23, 2013, at 8:51 AM, Tim Northover <tnorthover at apple.com> wrote:
> Hi Junbum,
>> I was aware that the definitions of target RegisterClass (outs) are different in t2LDRSB and t2LDRSB_PRE. While t2LDRSB uses rGPR, t2LDRSB_PRE uses GPR. I wonder if lr and pc are already prevented from being allocated in pre-indexing case, because of some register hint that is being enforced?
> They're not allocated during CodeGen because of the Reserved.set(…) calls in ARMBaseRegisterInfo.cpp.
> That said, this inconsistency is probably wrong anyway (or at best an approximation to reality) because it affects what the assembler supports. For example
> ldrsb sp, [r0]!
> is allowed, but
> ldrsb sp, [r0]
> is forbidden. I think they should both be UNPREDICTABLE (though this is an understandable error; support for unpredictable is in its early stages).
> Annoyingly, there is *some* distinction between the writeback and non-writeback versions. Fixing it properly might get hairy rather quickly.
“hairy” is an understatement. The way we model the ARM load/store instructions, especially the NEON ones, in LLVM is a bit of a mess. I tried digging in a while back and only got partway through before running out of time. It’s still on my list of cleanups I’d love to do someday...
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