<html><head><meta http-equiv="Content-Type" content="text/html charset=windows-1252"></head><body style="word-wrap: break-word; -webkit-nbsp-mode: space; -webkit-line-break: after-white-space;"><br><div><div>On May 23, 2013, at 8:51 AM, Tim Northover <<a href="mailto:tnorthover@apple.com">tnorthover@apple.com</a>> wrote:</div><br class="Apple-interchange-newline"><blockquote type="cite"><div style="letter-spacing: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px;">Hi Junbum,<br><br><blockquote type="cite">I was aware that the definitions of target RegisterClass (outs) are different in t2LDRSB and t2LDRSB_PRE. While t2LDRSB uses rGPR, t2LDRSB_PRE uses GPR. I wonder if lr and pc are already prevented from being allocated in pre-indexing case, because of some register hint that is being enforced?<br></blockquote><br>They're not allocated during CodeGen because of the Reserved.set(…) calls in ARMBaseRegisterInfo.cpp.<br><br>That said, this inconsistency is probably wrong anyway (or at best an approximation to reality) because it affects what the assembler supports. For example<br><span class="Apple-tab-span" style="white-space: pre;"> </span>ldrsb sp, [r0]!<br>is allowed, but<br><span class="Apple-tab-span" style="white-space: pre;"> </span>ldrsb sp, [r0]<br>is forbidden. I think they should both be UNPREDICTABLE (though this is an understandable error; support for unpredictable is in its early stages).<br><br>Annoyingly, there is *some* distinction between the writeback and non-writeback versions. Fixing it properly might get hairy rather quickly.<br></div></blockquote><div dir="auto"><br></div>“hairy” is an understatement. The way we model the ARM load/store instructions, especially the NEON ones, in LLVM is a bit of a mess. I tried digging in a while back and only got partway through before running out of time. It’s still on my list of cleanups I’d love to do someday...</div><div><br></div><div>-Jim</div><div><br><blockquote type="cite"><div style="letter-spacing: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px;"><br>Tim.<br>_______________________________________________<br>LLVM Developers mailing list<br><a href="mailto:LLVMdev@cs.uiuc.edu">LLVMdev@cs.uiuc.edu</a><span class="Apple-converted-space"> </span> <a href="http://llvm.cs.uiuc.edu/">http://llvm.cs.uiuc.edu</a><br><a href="http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev">http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev</a></div></blockquote></div><br></body></html>