[LLVMdev] Predicated Vector Operations

Jeff Bush jeffbush001 at gmail.com
Fri May 10 18:08:33 PDT 2013

On Fri, May 10, 2013 at 9:53 AM,  <dag at cray.com> wrote:
> Jeff Bush <jeffbush001 at gmail.com> writes:
>> Ah, I think I get it now.  This was mentioned earlier in the thread,
>> but it didn't click at the time. It sounds like I can do instruction
>> selection with a pattern like (omitting selection of the sources):
>> let Constraints = "$dst = $oldvalue" in {
>>     def MASKEDARITH : MyInstruction<
>>         (outs VectorReg:$dst),
>>         (ins MaskReg:$mask, VectorReg:$src1, VectorReg:$src2,
>> VectorReg:$oldvalue),
>>         "add $dst {$mask}, $src1, $src2",
>>         [(set v16i32:$dst, (vselect v16i1:$mask, (add v16i32:$src1,
>> v16i32:$src2), v16i32:$oldvalue))]>;
>> }
> Ok, but where does $oldvalue come from?  That is the trickty part as far
> as I can see and is why this isn't quite the same as handling
> two-address instructions.

I may be missing some important detail here, but I assumed $oldvalue
and $dst were just SSA names for the same variable.  For example,
given the following snippet for a compute kernel:

   if (x > 10)
       x = x - 10

If you wanted to run a bunch of parallel instances with each vector
lane representing an instance, I assume the IR would be something
roughly like (ignoring source selects for brevity):

   %mask = cmp gt %x1, 10
   %diff = sub %x1, 10
   %x2 = select %mask, %diff, %x1

At this point, %x1 is dead. %x1 and %x2 represent 'x' in the program above.

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