[LLVMdev] MnemonicAliases and side-effects
grosbach at apple.com
Mon Mar 25 14:54:23 PDT 2013
Short answer: No, that's not how assembly aliases work.
A MnemonicAlias is entirely a construct of the assembly parser. By the time anything that matches via the alias gets to parts of the toolchain that know anything about uses and defs, it's as-if there only ever were one instruction definition at all.
On Mar 25, 2013, at 10:08 AM, Muhammad Tauqir Ahmad <muhammad.t.ahmad at intel.com> wrote:
> I have a question about Instructions and MnemonicAliases.
> Let's say I have an instruction (an instruction prefix actually, in
> the X86 backend), and the instruction has 'Defs' and 'Uses' defined
> for it.
> If I define a MnemonicAlias from that instruction prefix to another,
> then do the 'Defs' and 'Uses' get "applied" to the alias as well?
> In other words, is it possible to define two instruction prefixes with
> the same "opcode" such that one prefix defines 'Defs' and 'Uses' while
> the other does not.
> - Muhammad Tauqir
> LLVM Developers mailing list
> LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu
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