[LLVMdev] Simpler types in TableGen isel patterns

Jakob Stoklund Olesen stoklund at 2pi.dk
Sat Mar 23 13:54:49 PDT 2013

On Mar 23, 2013, at 1:50 PM, Francois Pichet <pichet2000 at gmail.com> wrote:

> On Thu, Mar 21, 2013 at 2:26 PM, Jakob Stoklund Olesen <stoklund at 2pi.dk> wrote:
> When using register classes as proxies for types, it also becomes very difficult to support more than one legal type in a register class. If I were to entertain the heretic notion that an f32 might fit in a 32-bit register:
>   def GR32 : RegisterClass<"X86", [i32, f32], 32, ...
> TableGen explodes with a thousand type inference errors.
> How come the Hexagone backend is able to get away with that then?
> def IntRegs : RegisterClass<"Hexagon", [i32,f32], 32,

They have to use explicit type casts everywhere:

  def rr : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
                 !strconcat("$dst = ", !strconcat(OpcStr, "($b, $c)")),
                 [(set (i32 IntRegs:$dst), (OpNode (i32 IntRegs:$b),
                                                   (i32 IntRegs:$c)))]>;


-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20130323/da2d1f93/attachment.html>

More information about the llvm-dev mailing list