<html><head><meta http-equiv="Content-Type" content="text/html charset=iso-8859-1"></head><body style="word-wrap: break-word; -webkit-nbsp-mode: space; -webkit-line-break: after-white-space; "><br><div><div>On Mar 23, 2013, at 1:50 PM, Francois Pichet <<a href="mailto:pichet2000@gmail.com">pichet2000@gmail.com</a>> wrote:</div><br><blockquote type="cite"><div dir="ltr"><div class="gmail_extra"><div class="gmail_quote">On Thu, Mar 21, 2013 at 2:26 PM, Jakob Stoklund Olesen <span dir="ltr"><<a href="mailto:stoklund@2pi.dk" target="_blank">stoklund@2pi.dk</a>></span> wrote:<br>
<blockquote class="gmail_quote" style="margin: 0px 0px 0px 0.8ex; border-left-width: 1px; border-left-color: rgb(204, 204, 204); border-left-style: solid; padding-left: 1ex; position: static; z-index: auto; ">When using register classes as proxies for types, it also becomes very difficult to support more than one legal type in a register class. If I were to entertain the heretic notion that an f32 might fit in a 32-bit register:<br>
<br>
def GR32 : RegisterClass<"X86", [i32, f32], 32, ...<br>
<br>
TableGen explodes with a thousand type inference errors.<br><br></blockquote><div><br></div><div style="">How come the Hexagone backend is able to get away with that then?</div><div style=""><br></div><div style=""><div>def IntRegs : RegisterClass<"Hexagon", [i32,f32], 32,</div></div></div></div></div></blockquote><div><br></div><div>They have to use explicit type casts everywhere:</div><div><br></div><div><div> def rr : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c),</div><div> !strconcat("$dst = ", !strconcat(OpcStr, "($b, $c)")),</div><div> [(set (i32 IntRegs:$dst), (OpNode (i32 IntRegs:$b),</div><div> (i32 IntRegs:$c)))]>;</div><div><br></div><div>/jakob</div><div><br></div></div></div></body></html>