[LLVMdev] Instruction Constraints Question
cameron.mcinally at nyu.edu
Wed Jan 23 18:58:15 PST 2013
On Wed, Jan 23, 2013 at 5:06 PM, Cameron McInally <cameron.mcinally at nyu.edu>
> On Wed, Jan 23, 2013 at 4:40 PM, Tim Northover <t.p.northover at gmail.com>
>> >> It doesn't look like TableGen supports Constraints beyond EARLY_CLOBBER
>> >> and TIED_TO. We would need to add a constraint such as "$dst != $src1,
>> >> $dst != $mask, $src1 != $mask" to the current patterns to enforce the
>> >> rules.
>> > You can emulate such constraints via early clobbing. Just mark dst as
>> > early clobbing.
>> How would that (or any early clobbering) enforce $src1 != $mask? Or is
>> it a fortuitous side-effect of implementation?
> In this case, $src1 is also the destination register. A masked gather will
> merge the conditionally selected elements into the input vector.
Sorry, I was looking at the gather pattern and not at Dave's
example. EARLY_CLOBBER should be *sufficient*.
For a masked gather, all source operands are live entering the instruction.
No problem there.
For an unmasked gather, the mask and index vector are live entering the
instruction. The input vector can be undefined though, which leads to the
problem of having the index vector being reused as the destination. Marking
the destination as EARLY_CLOBBER should sort that out.
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