[LLVMdev] Instruction Constraints Question
cameron.mcinally at nyu.edu
Wed Jan 23 14:06:27 PST 2013
On Wed, Jan 23, 2013 at 4:40 PM, Tim Northover <t.p.northover at gmail.com>wrote:
> >> It doesn't look like TableGen supports Constraints beyond EARLY_CLOBBER
> >> and TIED_TO. We would need to add a constraint such as "$dst != $src1,
> >> $dst != $mask, $src1 != $mask" to the current patterns to enforce the
> >> rules.
> > You can emulate such constraints via early clobbing. Just mark dst as
> > early clobbing.
> How would that (or any early clobbering) enforce $src1 != $mask? Or is
> it a fortuitous side-effect of implementation?
In this case, $src1 is also the destination register. A masked gather will
merge the conditionally selected elements into the input vector.
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