[LLVMdev] Generating unusual instruction

Vikram Singh vsp1729 at gmail.com
Wed Jan 9 22:40:11 PST 2013

Thanks, I tried to go thru the Mips code to see the code related to the
branch implementation. But there are many fragments in the MipsInstrInfo.td
and also many Pat statements. Please help me in regard of these points.
1. I find it, as it seems to me, hard to refer Mips because I already have
taken Sparc code. Is there any way to modify Sparc code for eliminate SUBCC.
2. I find less literature on the .td file. for example consider
     [brcond (i32 (cond_op RC:$rs, RC:$rt)), bb:$offset, IIBranch]
    What is IIBranch.
3. What are these ZextLoad and the likes?


View this message in context: http://llvm.1065342.n5.nabble.com/Generating-unusual-instruction-tp53192p53427.html
Sent from the LLVM - Dev mailing list archive at Nabble.com.

More information about the llvm-dev mailing list