[LLVMdev] Generating unusual instruction

Dongrui She sarevokcc at gmail.com
Mon Jan 7 06:29:44 PST 2013


Have you try to directly describe such patterns in tblgen file? Like this:
(brcond (i32 (cond_op RC:$rs, RC:$rt)), bb:$offset)

MIPS backend does that. I also do this in my own backend, and seem to be
working fine.

On Mon, Jan 7, 2013 at 11:55 AM, Vikram Singh <vsp1729 at gmail.com> wrote:

> I have seen that most of the targets do comparison and branching
> in two separate instructions e.g. 'cmpl' followed by 'br' in x86 or the
> like.
> LLVM IR is also in same manner.
> I want to implement comparison+branching in one instruction like
>        beq r1, r2, .label   #if r1==r2 then jump to .label
> How to merge two instruction into one.
> Regards
> Vikram Singh
> --
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