[LLVMdev] Types in TableGen instruction selection patterns

[Jakob Stoklund Olesen]

On Apr 19, 2013, at 9:55 PM, Tom Stellard <tom at stellard.net> wrote:

> I'm going through the R600 target and converting all the patterns to the
> new syntax, and I've come across a pattern that I'm unable to convert:
> 
> class BitConvert <ValueType dt, ValueType st, RegisterClass rc> : Pat <
>  (dt (bitconvert (st rc:$src0))),
>  (dt rc:$src0)
>> ;
> 
> def : BitConvert <i32, f32, R600_Reg32>;
> 
> In this example R600_Reg32 is a register that can hold f32 or i32
> types, so bitconvert is a free operation.  Any suggestions for how to
> re-work this pattern?

It's a bit annoying, but COPY_TO_REGCLASS does the trick.

/jakob