[LLVMdev] Types in TableGen instruction selection patterns

[Tom Stellard]

On Sun, Mar 24, 2013 at 12:50:02PM -0700, Jakob Stoklund Olesen wrote:
> I have updated TableGen to support a new format for instruction selection patterns.
> 
> Before:
> 
>   def : Pat<(subc IntRegs:$b, IntRegs:$c), (SUBCCrr IntRegs:$b, IntRegs:$c)>;
> 
> After:
> 
>   def : Pat<(subc i32:$b, i32:$c), (SUBCCrr $b, $c)>;
> 
> Since the pattern matching happens on a DAG with type labels, not register classes, I think it makes more sense to specify types directly on the input patterns. The new syntax also helps avoid the problem where TableGen emits lots of type inference errors when multiple types are added to a register class.
> 
> In the output pattern, it is no longer necessary to duplicate the register classes or types of register operands.
> 
> For immediate operands, the 'imm' tag is still required:
> 
>   def : Pat<(subc i32:$b, simm13:$val), (SUBCCri $b, imm:$val)>;
> 
> 
> I would like for the old register class notation to go away eventually.
> 

Hi Jakob,

I'm going through the R600 target and converting all the patterns to the
new syntax, and I've come across a pattern that I'm unable to convert:

class BitConvert <ValueType dt, ValueType st, RegisterClass rc> : Pat <
  (dt (bitconvert (st rc:$src0))),
  (dt rc:$src0)
>;

def : BitConvert <i32, f32, R600_Reg32>;

In this example R600_Reg32 is a register that can hold f32 or i32
types, so bitconvert is a free operation.  Any suggestions for how to
re-work this pattern?

Thanks,
Tom