[LLVMdev] Proposal: New DAG node type for reciprocal operation
weimingz at codeaurora.org
Thu Sep 20 15:26:03 PDT 2012
In relaxed/fast math mode, if we can convert a/b to a * (1/b), we may get
more performance when (1) "b" is loop invariant or (2) arch has faster
reciprocal instruction (e.g. recipe/recips on ARM) or (3) arch has no
vector div, but has vector mul and recip.
So ,with this node type, a div node can be converted to a mul and a recip
when desired. Then, each arch can further lower the recip node. Even if the
arch has no recip support, allowing other passes to hoist "1/b" out of loop
may still be profitable.
It this feasible?
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