[LLVMdev] Need Help Understanding Operands in X86 MachineFunctionPass
criswell at illinois.edu
Tue Sep 11 10:41:48 PDT 2012
On 9/11/12 12:10 PM, Stephen Checkoway wrote:
> On Sep 11, 2012, at 10:57 AM, John Criswell wrote:
>> I'm working on an X86 MachineFunctionPass that adds prefetch instructions to a function. I have code that adds a "prefetchnta <constant address>" instruction to x86 32-bit code. What I want to do is to add a "prefetchnta <constant address>" instruction to x86_64 code.
> Given that you don't actually want to execute this instruction ever, is there a reason to even emit the instruction?
It's true that I don't want to emit the instruction, but it may be
easier to emit an instruction than to emit a constant into the
Also, I imagine that if I don't solve this problem with prefetchnta that
I might run into it again when I write some other machine-level
instrumentation. The prefetchnta is just a concrete example; more
generally, I just need to understand how the operands to the x86
instructions work in the LLVM code generator. I figure that if I
understand prefetchnta I'll have an easier time figuring out other
> Why not just stick your ID directly into the code and then jump beyond it. Executing the instruction causes a slow down and it requires a bunch of extra bytes. If you can live with a 32-bit ID, it'll take 4 bytes. If you go the prefetchnta (or any of the other prefetch instructions) route, then on the x86_64, it looks like you're going to have 2 bytes of opcode, a mod r/m byte, and 8 bytes of address and look something like 0f 18 00 dd cc bb aa 00 00 00 00 (I probably got the mod r/m byte wrong, it's a /0 for prefetchnta at any rate). That's just going to add extra pressure to the icache.
I think the instrumentation already adds a jump around the prefetchnta.
>> The code for adding the 32-bit instruction is:
> That's surprising to me. What are all of those registers and immediates for?
That is precisely my question. What do all of those register and
immediate arguments do?
-- John T.
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