[LLVMdev] Problem with PostRASchedulerList.cpp - advice wanted

[Gurd, Preston]

When you compile the attached file using

  llc -march=x86 -mcpu=atom sched-bug.ll -o -

The Post-RA scheduler changes the sequence

movl %ecx, (%esp)
     bsfl (%esp),%eax # this came from inline assembly code

to read

               bsfl (%esp),%eax # this came from inline assembly code
movl %ecx, (%esp)

This is an incorrect schedule, because it seems the scheduler is not aware that the memory load by the bsfl depends on  the memory store by the movl.

If you are familiar with the Post-RA scheduler works, then I would appreciate any suggestions you might have as to how I could fix this problem, such as by treating inline assembly code as a barrier or by including memory references in scheduling decisions.

Thanks,

Preston G

--
Preston Gurd <preston.gurd at intel.com>
  Intel Waterloo

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