[LLVMdev] Question on Fence Instruction

Duan, Yue Lu duan11 at illinois.edu
Wed Oct 17 07:21:40 PDT 2012

Thank you very much for the quick reply. I was trying to confirm what I did was correct. I did a test that could enable a simple way of sc-preserving compilation by inserting fences for every load/store instruction before any opts, applying standard opts and then removing them after assembly code generation. It turned out that such sc-preserving compilation only caused ~4% slowdown for 18 benchmarks on average on a Intel Xeon machine. The result surprised me a lot because it was reported that such naive way of compilation can cause 20% slowdown in a recent PLDI paper (they also use LLVM), so I posted this question. I will try to examine if the generated binary code really respects sc fences.

From: 陳韋任 (Wei-Ren Chen) [chenwj at iis.sinica.edu.tw]
Sent: Wednesday, October 17, 2012 9:00 AM
To: Duan, Yue Lu
Cc: llvmdev at cs.illinois.edu
Subject: Re: [LLVMdev] Question on Fence Instruction

On Tue, Oct 16, 2012 at 01:44:57PM +0000, Duan, Yue Lu wrote:
> Hi,
> I have a question with the latest released LLVM which supports Fence
> Instruction as IR. Say if I intentionally place a Sequentially Consistent Fence
> Instruction somewhere in the code, then would the other transformation passes
> that applied later respect the Fence and do not perform any reordering across
> it?

  In theory, all optimization passes should respect sc. If you find any
counter example, I think it's a bug.


Wei-Ren Chen (陳韋任)
Computer Systems Lab, Institute of Information Science,
Academia Sinica, Taiwan (R.O.C.)
Tel:886-2-2788-3799 #1667
Homepage: http://people.cs.nctu.edu.tw/~chenwj

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