[LLVMdev] LLVM Loop Vectorizer

Shuxin Yang shuxin.llvm at gmail.com
Fri Oct 5 10:33:17 PDT 2012

 >I think that the first step would be to expose Target Lowering 
Interface (TLI) to OPT's IR-level passes.

By "lowering", we assume the bitcode is more abstract than the machine 
code. However, in some situations, it is just opposite. For instance, 
some architectures support vectorization of 
min/max/saturated-{add,sub)/conditional-assignment/etc/../etc. We need 
to detect such machine dependent patterns, and *PROMOTE* the bitcode 
into right forms before we are able to vectorize them. How to deal with 
this situation?


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