[LLVMdev] Compiling for several operand memories

[Ivan Llopard]

Hi Magnus,

We've the same situation in our back-end, two memories with its 
corresponding loads/stores each one. In order to select between two 
different loads (and stores), we have defined two complex patterns 
requiring its parent node (SDNPWantParent) so we can get the address 
space number.

def MEMA : ComplexPattern<iPTR, 3, "SelectAddrA", [], [SDNPWantParent]>;
def MEMB : ComplexPattern<iPTR, 3, "SelectAddrB", [], [SDNPWantParent]>;

Then in SelectAddrA/B, you can specify the address space number for 
which you want your select function to work on.

bool SelectAddrA(SDNode *Parent, ...) {
...
AddrSpace = cast<MemSDNode>(Parent)->getPointerInfo().getAddrSpace();
if (AddrSpace !=A)
     return false;
...
}

Hope this helps!

Regards,
Ivan

On 06/11/2012 21:21, Magnus wrote:
> Have not gotten much further on this, I can so far only use one memory with
>
> (for example)
> def LDr1   : F1<  (outs GenRegs:$dst), (ins GenRegs:$addr),
>                    "ld*0* $dst, ($addr)",
>                    [(set GenRegs:$dst, (load GenRegs:$addr))],IIGenLoad>;
>
> and
>
> def LDrr   : F1<  (outs GenRegs:$dst), (ins MEMrr:$addr),
>                    "ld*0* $dst, ($addr)",
>                    [(set GenRegs:$dst, (load ADDRrr:$addr))],IIGenLoad>;
>
> What i want to do is to be able to also have these two:
>
> def LDr1   : F1<  (outs GenRegs:$dst), (ins GenRegs:$addr),
>                    "ld*1* $dst, ($addr)",
>                    [(set GenRegs:$dst, (load GenRegs:$addr))],IIGenLoad>;
>
> and
>
> def LDrr   : F1<  (outs GenRegs:$dst), (ins MEMrr:$addr),
>                    "ld*1* $dst, ($addr)",
>                    [(set GenRegs:$dst, (load ADDRrr:$addr))],IIGenLoad>;
>
> but they should only match when accessing data structres whose address space
> attribute is set to 1.
> Can I use the predicate field in the instruction class to achieve this? If
> so, how :/ ?
>
>   -Magnus
>
>
>
> --
> View this message in context: http://llvm.1065342.n5.nabble.com/Compiling-for-several-operand-memories-tp49698p50817.html
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