[LLVMdev] Compiling for several operand memories

[Magnus]

Have not gotten much further on this, I can so far only use one memory with 

(for example)
def LDr1   : F1<  (outs GenRegs:$dst), (ins GenRegs:$addr),
                  "ld*0* $dst, ($addr)",
                  [(set GenRegs:$dst, (load GenRegs:$addr))],IIGenLoad>;

and

def LDrr   : F1<  (outs GenRegs:$dst), (ins MEMrr:$addr),
                  "ld*0* $dst, ($addr)",
                  [(set GenRegs:$dst, (load ADDRrr:$addr))],IIGenLoad>;

What i want to do is to be able to also have these two:

def LDr1   : F1<  (outs GenRegs:$dst), (ins GenRegs:$addr),
                  "ld*1* $dst, ($addr)",
                  [(set GenRegs:$dst, (load GenRegs:$addr))],IIGenLoad>;

and

def LDrr   : F1<  (outs GenRegs:$dst), (ins MEMrr:$addr),
                  "ld*1* $dst, ($addr)",
                  [(set GenRegs:$dst, (load ADDRrr:$addr))],IIGenLoad>;

but they should only match when accessing data structres whose address space
attribute is set to 1.
Can I use the predicate field in the instruction class to achieve this? If
so, how :/ ?

 -Magnus



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