[LLVMdev] Half Float fp16 Native Support

[Tim Northover]

Hi Nikos

> and when i try to call llc  produces this error
>
> LLVM ERROR: Cannot select: 0x234bab0: f16 = fadd 0x234b8b0, 0x234c2b0
> [ORD=9] [ID=29]

This error suggests things are working on the generic LLVM side (as
I'd expect). It's what I'd expect to see for your code snippet if
there wasn't a target-specific pattern that could handle the addition
properly and select it to a valid instruction. What patterns do you
have for f16 addition so far?

If there's really nothing obviously wrong with them, the next step is
probably to delve into what the DAG matcher is doing behind the
scenes. If you give llc the option "-debug" it should tell you what
patterns it's tried to match against the fadd and where they failed.
If you cross-reference this with the table in
build/lib/Target/XXX/XXXGenDAGISel.inc you should be able to work out
where things are going wrong. (There are comments giving what each
original pattern was *below* the check that'll fail in each case).

> As we are working on half float fp16 support in LLVM are there any plans to
> support it on the main trunk ?

As I sort of implied, it's mostly down to the targets implementing
support now. The generic LLVM code doesn't need to do much with it. I
suppose there could be parts of the DAG combiner that assume
float/double or calls out to runtime library support functions that
aren't implemented, but that's not what you're hitting here. In fact
I'd expect most of the generic code to simply not care whether the
float it was considering is 16/32/64-bits wide and Just Work for
16-bit ones.

Hope this helps.

Tim.