[LLVMdev] Predicate registers/condition codes question

[Duncan Sands]

Hi Sebastian,

On 04/06/12 18:23, Sebastian Pop wrote:
> Salut Duncan,
>
> On Sun, Jun 3, 2012 at 7:55 AM, Duncan Sands<baldrick at free.fr>  wrote:
>> Hi,
>>
>>>> The problem is that the existing integer arithmetic operations on i8
>>>> are not legal to be executed on the predicate registers (i.e., clang
>>>> would generate an i8 expression for the addition of two char
>>>> variables.)  Hexagon cannot do integer arithmetic operations using the
>>>> predicate registers.
>>
>> so what can you actually do with predicate registers?
>
> Hexagon can use predicate registers to do boolean arithmetic,
> and code predication.

maybe you can represent the result as a "flag" rather than a register,
c.f. x86 eflags.  I don't recall how this works exactly, hopefully someone
else will chime in and explain how this works, and if this makes any sense.

Ciao, Duncan.