[LLVMdev] No more TargetFlags on MO_Register MachineOperands

[Tom Stellard]

On Mon, Aug 20, 2012 at 04:30:13PM -0700, Jakob Stoklund Olesen wrote:
> All,
> 
> The code generator operand class, MachineOperand, has an 8-bit TargetFlags field that the individual targets can use as they please. X86 and ARM use it to encode linker magic on symbol operands.
> 
> It has been mentioned a couple of times on this list that it is not safe to use TargetFlags on register operands. This is because many target-independent passes are manipulating register operands when the code is in SSA form, and they can't always preserve flags they don't understand.
> 
> I am going to add an assertion that no target flags are added to register operands. This will prevent subtle bugs when flags disappear, and it will free up some space in the MachineOperand struct layout.
> 
> None of the in-tree targets need this, external targets should probably be using extra immediate operands to encode  register flags.
>

Hi,

I've been working on replacing the MachineOperand flags in the R600
backend with immediate operands, but I can't figure out how to modify
the instruction patterns to make this work.  For example, I have the class:

class R600_1OP <bits<32> inst, string opName, list<dag> pattern,
                InstrItinClass itin = AnyALU> :
  InstR600 <inst,
          (outs R600_Reg32:$dst),
          (ins R600_Reg32:$src, R600_Pred:$p, i32imm:$flags),
          !strconcat(opName, " $dst, $src ($p)"),
          pattern,
          itin
  >;

And an instruction def:

def CEIL : R600_1OP <
  0x12, "CEIL",
  [(set R600_Reg32:$dst, (fceil R600_Reg32:$src))]
>;

Tablegen fails to compile this with an error: "Operand $flag does not
appear in the instruction pattern"

Is there some way I can have this pattern initialize the $flag operand
to 0?

Thanks,
Tom