[LLVMdev] VLIW code generation for LLVM backend

[Sergei Larin]

Yang, 

  There is work currently underway to add SW pipelining and some sort of
global scheduling to Hexagon, but if there is some interest to it from other
targets, it would be helpful to know. What is your involvement with this?

Sergei Larin

--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum.

> -----Original Message-----
> From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu]
> On Behalf Of Triple Yang
> Sent: Wednesday, July 25, 2012 3:56 AM
> To: llvmdev at cs.uiuc.edu
> Subject: [LLVMdev] VLIW code generation for LLVM backend
> 
> Hi,
> 
> It seems the only one VLIW target Hexagon in LLVM 3.2 devel uses a
> straightforward way to emit its VLIW-style asm codes.
> It uses a list scheduler to schedule on DAG and a simple packetizer to
> wrap the emitted asm instructions.
> Both scheduling and packetizing work on basic blocks.
> 
> so, is there any plan to implement better optimization methods such as
> trace scheduling, software pipelining, ...
> or  is it already going on?
> 
> Best regards.
> 
> --
> 杨勇勇 (Yang Yongyong)