[LLVMdev] VLIW code generation for LLVM backend

[Triple Yang]

Larin,

Thank you for telling me about this.

Our lab is planning to design a VLIW DSP and has to make a choice
between GCC and LLVM, for which I take responsibility.
As we all know that GCC's codes possess a long history and has a
somewhat bad learning curve, I suggest choosing LLVM.

It seems now the only drawback is its poor support for VLIW
architecture. And so if we can count on LLVM's support for VLIW in a
near future, we will choose LLVM as the compiler infrastructure
without the least hesitation.

Can I do any help for this underway work?

Regards.

2012/8/8 Sergei Larin <slarin at codeaurora.org>:
> Yang,
>
>   There is work currently underway to add SW pipelining and some sort of
> global scheduling to Hexagon, but if there is some interest to it from other
> targets, it would be helpful to know. What is your involvement with this?
>
> Sergei Larin
>
> --
> Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum.
>
>> -----Original Message-----
>> From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu]
>> On Behalf Of Triple Yang
>> Sent: Wednesday, July 25, 2012 3:56 AM
>> To: llvmdev at cs.uiuc.edu
>> Subject: [LLVMdev] VLIW code generation for LLVM backend
>>
>> Hi,
>>
>> It seems the only one VLIW target Hexagon in LLVM 3.2 devel uses a
>> straightforward way to emit its VLIW-style asm codes.
>> It uses a list scheduler to schedule on DAG and a simple packetizer to
>> wrap the emitted asm instructions.
>> Both scheduling and packetizing work on basic blocks.
>>
>> so, is there any plan to implement better optimization methods such as
>> trace scheduling, software pipelining, ...
>> or  is it already going on?
>>
>> Best regards.
>>
>> --
>> 杨勇勇 (Yang Yongyong)
>
>



-- 
杨勇勇 (Yang Yongyong)