[LLVMdev] Some questions on SelectionDAG

Villmow, Micah Micah.Villmow at amd.com
Fri Sep 2 09:45:43 PDT 2011

From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] On Behalf Of Zakk
Sent: Friday, September 02, 2011 3:15 AM
To: llvmdev
Subject: [LLVMdev] Some questions on SelectionDAG

Hi, all

I am studying the ARM backend on SelectionDAG, I have some following questions:

1. Each operator of SDNode in SelectionDAG is required to be defined by SDNode<ISD::XXX,XXX,XXX> in .td file, right?
But several operators are not defined in .td file, why? (e.g., ISD::BR_CC, ISD::CopyToReg, ISD::AssertSext)
[Villmow, Micah] These are the standard nodes, please see the ISDOpcodes.h file in the  include/llvm/CodeGen directory.

2. The MVT::glue value is used to ensure two nodes are scheduled together and in order.
In the other word, we can't insert any instruction of them in the scheduling, is it correct?

3. In the ARMISelLowering constructor, it sets the callback function with
setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
My question is ARM don't support MVT::i1 registerclass, why should it determine this operation with MVT::i1 value?
[Villmow, Micah] Promote means the instruction that have a return value of that type extend to the next largest supported type.

Can anyone tell me?
Thank you very much.

Best regards,

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