[LLVMdev] LLVM and VHDL simulation
jonas.baggett at hefr.ch
Thu Oct 6 23:29:45 PDT 2011
I have posted the following message at the wrong place, sorry.
Thanks for your answers.
In one year, I am going to have something like a semester project.
The idea I have for this project would be to create (for simulation only) a
VHDL front-end to LLVM, compile some VHDL code with the newly created
compilator and also with a commercial compilator and simulator and compare the
performance of both simulations. I won't have the time to do a full VHDL
support, but if I implement at least entities/architectures, concurrent
statements, processes, integer and/or real and boolean types, that should be
enough to do the comparison. Maybe after the project, I will continue to work
on the VHDL front-end. The main point of this project will be to see what LLVM
could bring in term of performances and ease of developpement. This project has
still to be accepted, so I am not 100% sure that I will do this project. I also
found a tutorial (http://llvm.org/docs/tutorial/) that can help me to
familiarize with LLVM before I will do this project (if I will).
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