[LLVMdev] Instr Description Problem of MCore Backend

[zhangzuyu]

Hi,

I have another puzzle.

In SPARC, load / store instructions form as below:

def MEMri : Operand<i32> {
    let PrintMethod = "printMemOperand";
    let MIOperandInfo = (ops IntRegs, i32imm);
}

def ADDRri : ComplexPattern<i32, 2, "SelectADDRri", [frameindex], []>;

def LDSBri : F3_2<3, 0bxxxxx,
                                   (outs IntRegs:$dst),
                                   (ins MEMri:$addr),
                                   "ldsb [$addr], $dst",
                                   [(set IntRegs:$dst, (sextloadi8
ADDRri:$addr))]>;

def STBri : F3_2<3, 0bxxxx,
                             (outs), (ins MEMri:$addr, IntRegs:$src),
                             "stb $src, [$addr]",
                             [(truncstorei8 IntRegs:$src, ADDRri:$addr)]>;


I means that in Sparc, the memory address in ld/st instruction is one
operand, but in MCore, ld.b, which means load byte, forms as "ld.b Rz, (Rx,
Disp)". It means that move MEM[Rx + unsigned Imm4 << 1] to Rz. Disp is
obtained by taking the Imm4 field, scaling by the size of the load, and
zero-extending.

  def disp : Operand<i32> {
      let PrintMethod = "printZExtConstOperand<4>";
     // I knew it's wrong code, I need to shift left by {0, 1, 2} here,
     // and then zero-extend.
     // 0 for word, 1 for byte, and 2 for halfword.
  }

  def LDB : MARc4<0xa,
                            (outs GPRs:$Rz), (ins GPRs:$Rx, disp:$Imm4),
                                 "ld.b $Rz, ($Rx, $Imm4)",
        // how do I use $Imm4 to form a $Disp by shifting left once?
           [(set GPRs:$Rz, (loadi8 (add GPRs:$Rx, uimm4:$Imm4)))]>;
        // and how do I use ComplexPattern to form a memory address?

STB means MEM[Rx + unsigned Imm4 << 1] <- Rz

  def STB : MARc4<0xb,
                              (outs), (ins GPRs:$Rz, disp:$Imm4. GPRs:$Rx),
                              "st.b $Rz, ($Rx, $Imm4)",
               [(truncstorei8 GPRs:$Rz, (add GPRs:$Rx, uimm4:$Imm4))]>;
// how to deal with uimm4? I have no idea to construct it as a calculated
memory address.

In MCore, Memory access to unsigned byte-sized data is directly supported
through the ld.b(load byte) and st.b (store byte) instructions. Signed
byte-sized access requires a sextb (sign extension) instruction after the
ld.b. That's why I use loadi8 instead of zextloadi8 in Sparc.

Thanks a lot!

On Thu, Jun 23, 2011 at 9:51 PM, Anton Korobeynikov <anton at korobeynikov.info
> wrote:

> Hello
>
> > Finally, I don't know how to describe following instructions in
> > MCoreInstrInfo.td, because of its variable ins/outs. Or what other files
> > should I use to finish this description?
> Do you need the isel support for them? If yes, then you should custom
> isel them. iirc ARM and SystemZ backends have similar instructions,
> while only the first one supports full isel for them. In short: you
> should recognize the consecutive loads / stores and turn them into
> load/store multiple.
>
> Yes, I would implement whole back-end to assembly code printing.


> If you just need the have assembler support, then you don't need to
> specify the exact operands there (for "Q" instructions), since they
> are fixed. Just provide the list of used / clobbered instructions.
>
> Yeah, It's a good idea!


> --
> With best regards, Anton Korobeynikov
> Faculty of Mathematics and Mechanics, Saint Petersburg State University
>



-- 
Yours truly,
Zhang Zuyu(张祖羽)

-----------------------------------------------------------
College of Computer Science and Technology, Harbin Engineering University
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