Hi,<div><br></div><div>I have another puzzle.</div><div><br></div><div>In SPARC, load / store instructions form as below:</div><div><br></div><blockquote class="webkit-indent-blockquote" style="margin: 0 0 0 40px; border: none; padding: 0px;">
<div>def MEMri : Operand<i32> {</div><div> let PrintMethod = "printMemOperand";</div><div> let MIOperandInfo = (ops IntRegs, i32imm);</div><div>}</div><div><br></div><div>def ADDRri : ComplexPattern<i32, 2, "SelectADDRri", [frameindex], []>;</div>
<div><br></div><div>def LDSBri : F3_2<3, 0bxxxxx,</div><div> (outs IntRegs:$dst), </div><div> (ins MEMri:$addr),</div><div> "ldsb [$addr], $dst",</div>
<div> [(set IntRegs:$dst, (sextloadi8 ADDRri:$addr))]>;</div><div><br></div><div>def STBri : F3_2<3, 0bxxxx,</div><div> (outs), (ins MEMri:$addr, IntRegs:$src),</div>
<div> "stb $src, [$addr]",</div><div> [(truncstorei8 IntRegs:$src, ADDRri:$addr)]>;</div></blockquote><div><br></div><div>I means that in Sparc, the memory address in ld/st instruction is one operand, but in MCore, ld.b, which means load byte, forms as "ld.b Rz, (Rx, Disp)". It means that move <span class="Apple-style-span" style="background-color: rgb(255, 255, 102);">MEM[Rx + unsigned Imm4 << 1]</span> to Rz. Disp is obtained by taking the Imm4 field, scaling by the size of the load, and zero-extending.</div>
<div><br></div><div> def disp : Operand<i32> {</div><div> let PrintMethod = "printZExtConstOperand<4>";</div><div><span class="Apple-style-span" style="background-color: rgb(255, 255, 102);"> // I knew it's wrong code, I need to shift left by {0, 1, 2} here,</span></div>
<div><span class="Apple-style-span" style="background-color: rgb(255, 255, 102);"> // and then zero-extend.</span></div><div><span class="Apple-style-span" style="background-color: rgb(255, 255, 102);"> // 0 for word, 1 for byte, and 2 for halfword.</span></div>
<div> }</div><div><br></div><div> def LDB : MARc4<0xa,</div><div> (outs GPRs:$Rz), (ins GPRs:$Rx, <span class="Apple-style-span" style="background-color: rgb(255, 255, 102);">disp:$Imm4</span>),</div>
<div> "ld.b $Rz, ($Rx, <span class="Apple-style-span" style="background-color: rgb(255, 255, 102);">$Imm4</span>)",</div><div> <span class="Apple-style-span" style="background-color: rgb(255, 255, 102);">// how do I use $Imm4 to form a $Disp by shifting left once?</span></div>
<div> [(set GPRs:$Rz, (loadi8 (<span class="Apple-style-span" style="background-color: rgb(255, 255, 102);">add GPRs:$Rx, uimm4:$Imm4</span>)))]>;</div><div> <span class="Apple-style-span" style="background-color: rgb(255, 255, 102);">// and how do I use ComplexPattern to form a memory address?</span></div>
<div><br></div><div>STB means MEM[Rx + unsigned Imm4 << 1] <- Rz</div><div><br></div><div> def STB : MARc4<0xb,</div><div> (outs), (ins GPRs:$Rz, disp:$Imm4. GPRs:$Rx),</div><div>
"st.b $Rz, ($Rx, $Imm4)",</div><div> [(truncstorei8 GPRs:$Rz, (add GPRs:$Rx, <span class="Apple-style-span" style="background-color: rgb(255, 255, 102);">uimm4</span>:$Imm4))]>;</div>
<div><span class="Apple-style-span" style="background-color: rgb(255, 255, 102);">// how to deal with uimm4? I have no idea to construct it as a calculated memory address.</span></div><div><br></div><div>In MCore, Memory access to unsigned byte-sized data is directly supported through the ld.b(load byte) and st.b (store byte) instructions. Signed byte-sized access requires a sextb (sign extension) instruction after the ld.b. That's why I use loadi8 instead of zextloadi8 in Sparc.</div>
<div><br></div><div>Thanks a lot!</div><div><br><div class="gmail_quote">On Thu, Jun 23, 2011 at 9:51 PM, Anton Korobeynikov <span dir="ltr"><<a href="mailto:anton@korobeynikov.info">anton@korobeynikov.info</a>></span> wrote:<br>
<blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex;">Hello<br>
<div class="im"><br>
> Finally, I don't know how to describe following instructions in<br>
> MCoreInstrInfo.td, because of its variable ins/outs. Or what other files<br>
> should I use to finish this description?<br>
</div>Do you need the isel support for them? If yes, then you should custom<br>
isel them. iirc ARM and SystemZ backends have similar instructions,<br>
while only the first one supports full isel for them. In short: you<br>
should recognize the consecutive loads / stores and turn them into<br>
load/store multiple.<br>
<br></blockquote><div>Yes, I would implement whole back-end to assembly code printing.</div><div> </div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex;">
If you just need the have assembler support, then you don't need to<br>
specify the exact operands there (for "Q" instructions), since they<br>
are fixed. Just provide the list of used / clobbered instructions.<br>
<font color="#888888"><br></font></blockquote><div>Yeah, It's a good idea!</div><div> </div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex;"><font color="#888888">
--<br>
With best regards, Anton Korobeynikov<br>
Faculty of Mathematics and Mechanics, Saint Petersburg State University<br>
</font></blockquote></div><br><br clear="all"><br>-- <br><div><span style="font-family:arial, sans-serif;font-size:11px;background-color:rgb(255, 255, 255)">Yours truly,</span><br>Zhang Zuyu(张祖羽)<br><br>-----------------------------------------------------------<br>
College of Computer Science and Technology, Harbin Engineering University</div>
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