[LLVMdev] LLVM Scheduler and Itinieraries: Negative latency?

Anton Korobeynikov anton at korobeynikov.info
Thu Apr 14 11:09:58 PDT 2011

Hello Magnus,

> I am trying to model a fairly simple five stage pipelined processor.

> The problem is that some instructions need the last stage (write back) to be
> finished so the correct operand is selected for a following instruction in
> stage 3.
Ok, this is pretty typical.

> machine cycles and higher values for when the result is ready (3) and when
> the operands are referenced (2) are showed. Do you have any hints on what I
> am doing wrong, since the example seem to show that this "negative latency"
> should work?
So, in your case the operands are read in the second cycle, then
several cycles the instruction occupies the functional unit and after
this at some cycle the results are written back. Is this correct?

If yes, then I think you should model stuff with two stages. First
stage will be "issue" with 1 cycle latency Second stage will be the
actual "execution unit", for which you can have, say, 1 cycle duration
of the stage and operands read in the beginning of the stage and
available at, say, 2 cycle from the beginning of the stage.

You might want to look into ARM backend as an example of target with
rather complex scheduling.

With best regards, Anton Korobeynikov
Faculty of Mathematics and Mechanics, Saint Petersburg State University

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