[LLVMdev] GSoC 2011: Fast JIT Code Generation for x86-64

Viktor Pavlu vpavlu at gmail.com
Tue Apr 5 02:56:51 PDT 2011

On Mon, Apr 4, 2011 at 9:50 PM, Eric Christopher <echristo at apple.com> wrote:
> On Apr 1, 2011, at 6:53 AM, Viktor Pavlu wrote:
>> [...] Although most optimizations are turned off
>> already and the FastISel instruction selector is used, the "fast" path
>> for first-time code generation is still the bottleneck [...]
> This is effectively what fastisel was created for - there are just IR
> constructs that don't go through that path. The idea is that fastisel
> will get most of the IR and everything that'd be really hard we just
> punt to the DAG. I imagine running more things through fastisel would
> help.

To me, increasing coverage of the FastISel seemed more involved than
directly emitting opcodes to memory, with a lesser outlook on
reducing overhead.

> That won't help the slow register allocation problem though - even
> the fast allocator is pretty slow. I haven't seen what your plan
> is for register allocation or were you planning on just using a few
> registers in defined ways?

My first idea was to implement a linear scan allocator integrated
into the code generation pass.

> Also, X86CodeEmitter.cpp is going away to be replaced with the MC
> emitters.

Yes, I remember reading about this on the mailing list.
With our simulator generators we are still living in 2.2/2.6 land,
though, but we will change that.

X86CodeEmitter was only meant to indicate that in my intended fast
path there is nothing in between the LLVM-IR passes and the final
emission of the code, i.e. an LLVM-IR pass that produces x86-64.

- Viktor

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