[LLVMdev] GSoC 2011: Fast JIT Code Generation for x86-64

[Eric Christopher]

On Apr 1, 2011, at 6:53 AM, Viktor Pavlu wrote:

> I currently work on generating fast cycle-accurate simulators[2]. For
> this, our institute has implemented a two-part adaptive compilation
> scheme using the LLVM-JIT. Although most optimizations are turned off
> already and the FastISel instruction selector is used, the "fast" path
> for first-time code generation is still the bottleneck of the
> simulators. This is for the largest part due to the SelectionDAG
> instruction selection process, hence the motivation for a simpler,
> two-pass code generator.

This is effectively what fastisel was created for - there are just IR
constructs that don't go through that path. The idea is that fastisel
will get most of the IR and everything that'd be really hard we just
punt to the DAG. I imagine running more things through fastisel would
help.

That won't help the slow register allocation problem though - even
the fast allocator is pretty slow. I haven't seen what your plan
is for register allocation or were you planning on just using a few
registers in defined ways?

Also, X86CodeEmitter.cpp is going away to be replaced with the MC
emitters.

-eric