[LLVMdev] Register design decision for backend

[Borja Ferrer]

 Indeed, if you remove the i16 regs registration by removing the call to
addRegisterClass() it works as expected. But that implies some other
problems:

You cannot pass i16/32/64 arguments to functions or return data using the
register pairs (atm i've only implemented LowerReturn and LowerFormalArgs
for testing trivial functions).
   Passing arguments in i8 regs work as expected, BUT, LLVM wont match
potential 16bit instruction patterns because data is contained in 8 bit regs
making code twice as big. For example, one 16 bit instruction is copying
between reg pairs, so as result of this you get 2 8bit moves instead of 1
16bit move. I guess i could fold this manually, but i would have to do this
for every other 16bit instructions, so i find this a bit inefficient. From
these results i find that once you remove the addRegisterClass() call the
i16 reg class becomes useless.

On the other side, the original problem again:
If i receive input args inside register pairs LLVM cant expand the i16 add
into an add/adde combination.

I could only work with 8 bit regs and fold somehow patterns into a 16 bit
instr but replicated for every 16 bit instruction, but i want to know if
there's a better solution for this since i find it too hacky and artificial.

Thanks for your patience.

(PS: sorry for the dup, but i sent the reply to your personal account
instead of to the list.)
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