[LLVMdev] Register design decision for backend

[Jakob Stoklund Olesen]

On Sep 1, 2010, at 8:57 AM, Borja Ferrer wrote:

> Thanks for the reply Jakob, good to know that my assumption that LLVM would split regs into smaller subregs is confirmed to be too optimistic. It would be nice if this case could be handled by LLVM, basically trying to split regs and see if patterns match with the splitted regs before giving an error.
> 
> About the transformation you mentioned in the selection DAG phase, that was my initial question, how to do it. I dont know if you meant to customize each arithmetic and logical operation with setOperationAction() or if there is way to just split regs and let LLVM handle the rest, so if you could expand a bit more on how to do it that would be great :) 
> I havent seen any other backend doing this because they all have instructions that are able to work with their widest regs, but my case is different because im working with register pairs and machine instructions can only work with the pair parts.

First of all, note that if you don't tell TargetLowering about your i16 register class with addRegisterClass(), it synthesizes i16 and i32 operations just fine. The register splitting, you are talking about is already there.

If you do add your i16 register class, TargetLowering is going to assume that it supports normal operations like add and sub. You must tell it that they are not available for i16 using setOperationAction().

Do some experiments with trivial functions, and see what happens.

/jakob