[LLVMdev] ARM Intruction Constraint DestReg!=SrcReg patch?

[maarten faddegon]

Hi,

I am using a cross compiler to compiler for the arm5 architecture. For
this architecture it is not allowed that a destination register is also
used as source register.
In 2007 a patch was discussed at the mailing list, however my compiler
still is producing this result. Does anyone know if this patch is
actually applied?

* I use the following arguments:
llvm-gcc -mfpu=vfp -mlittle-endian -mfloat-abi=softfp -march=armv5 -S
-O3 foo.c -S -o foo.s
* Attached to this document foo.c and the resulting foo.s. Please, take
note of the illegal instruction mul r0, r0, r2 at line 18.
* The patch is discussed at:
http://www.mail-archive.com/llvm-commits@cs.uiuc.edu/msg14069.html
* llvm-gcc --version
llvm-gcc (GCC) 4.2.1 (Based on Apple Inc. build 5658) (LLVM build)
Copyright (C) 2007 Free Software Foundation, Inc.

kind regards,
  Maarten Faddegon
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	.syntax unified
	.cpu arm10tdmi
	.eabi_attribute 10, 2
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.file	"foo.c"
	.text
	.globl	foo
	.align	2
	.type	foo,%function
foo:
	ldr	r1, .LCPI0_0
	ldr	r0, [r1]
	mov	r2, #123
	mul	r0, r0, r2
	mov	r2, #15
	orr	r2, r2, #15, 24
	add	r0, r0, #114, 30
	and	r0, r0, r2
	str	r0, [r1]
	bx	lr
	.align	2
.LCPI0_0:
	.long	bar
.Ltmp0:
	.size	foo, .Ltmp0-foo

	.type	bar,%object
	.comm	bar,4,4

	.ident	"GCC: (GNU) 4.2.1 (Based on Apple Inc. build 5658) (LLVM build)"