[LLVMdev] Default behavior of DeadMachineInstructionElim deletes all instructions

[Jakob Stoklund Olesen]

On May 3, 2010, at 10:21 AM, Villmow, Micah wrote:

> Jakob, 
> Here is my implementation of getAllocatableSet:
> BitVector 
> AMDILRegisterInfo::getAllocatableSet(const MachineFunction& MF,
> 		const TargetRegisterClass *RC = NULL) const
> {
> 	BitVector Allocatable(getNumRegs());
> 	Allocatable.clear();
> 	return Allocatable;
> }

Well, there's your problem.

BitVector::clear() resets the size to 0, and callers of getAllocatableSet expect a bit per physical register.

Please add an assert(NonAllocatableRegs.size() >= TRI->getNumRegs()) to DeadMachineInstructionElim.

/jakob