[LLVMdev] SelectionDAG legality: isel creating cycles

[David Greene]

On Monday 22 February 2010 10:31:24 David Greene wrote:

> The fundamental issue is that the DAG originally looked like this:
>
> MIN
>   LOAD B
>     PREFETCH
>       Chain from LOAD A
>   LOAD A

Actually, it looked like this:

MIN
  LOAD B
    Chain from PREFETCH
      Chain from LOAD A
    NULL
  LOAD A
    Chain from ENTRY
    Some Addressing

LOAD B is from NULL because this is a bugpoint-reduced testcase, so that's not 
an issue.

Just wanted to clarify in case someone was wondering about this.

                                                 -Dave