[LLVMdev] RFC: AVX Pattern Specification [LONG]

David Greene dag at cray.com
Tue May 5 09:31:03 PDT 2009

On Tuesday 05 May 2009 01:02, Evan Cheng wrote:

> I think it makes sense for isel to use HW cost (instruction latency,
> code size) as a late tie breaker. In that case, shouldn't cost be part
> of instruction itinerary?

What latency?  Each implementation has its own quirks and LLVM must be
flexible enough to handle them.  So cost needs to be a function of
the CPU type as well as the instruction.

We do need a better cost/priority mechanism than AddedComplexity (the naming 
alone of that is very confusing).  Perhaps we can have some base cost values
per instruction and allow each CPU type to override them.


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